The present invention relates to a semiconductor device having a 4F2 structure and a method for manufacturing the same.
As the integration of semiconductor devices has been increased, a two-dimensional area occupied by each unit cell has been decreased. With the decrease of the area occupied by the unit cell, various methods have been introduced to form a transistor, a bit line, a word line and a capacitor in a limited area.
As one of those methods, a semiconductor device having a vertical transistor has been suggested. In such a semiconductor device, a source region and a drain region of the vertical transistor are arranged upward and downward in an active region so that a vertical channel may be formed.
In the vertical transistor, a gate is formed on sidewalls of a silicon pillar included in the active region. With respect to the gate, the source region is formed at an upper side of the silicon pillar, and the drain region is formed in a silicon substrate disposed below the silicon pillar. In the semiconductor device including this vertical transistor, a cell scheme is reduced to a 4F2 structure, resulting in increasing a net die. However, a manufacturing process of the semiconductor device including the vertical transistor is complicated.